PLD/FPGA Workshop 2.5
[Hackerspace.gr external link]
|Wed 16 Oct 2013 19:30||Hackerspace.gr|
|Wed 16 Oct 2013 21:30||User:Skmp|
What about conditions?
Stuff for review
sdlcore @ github
verilog WIP @ github
ideas for the workshop
- Implement conditional branches
- wire up vram
- mayhaps integrate old vga controller?
- vga doesn't fit :'(
- Reduced to 2bpp for now
- The core runs for quite a bit, but some bugs prevent proper operation
- We have some (corrupted) vga output!
Also checkout The main project page