PLD/FPGA Workshop 2.6

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Simple soc logo.jpg

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Starts Organizer
Wed 23 Oct 2013 19:30
Ends Event Owner
Wed 23 Oct 2013 21:30 User:Skmp

We love glitches

Stuff for review

sdlcore @ github

verilog WIP @ github


  • Fixed vga output, centered, with colored border
  • Debugged the vram contents & vga out on the simulator, everything seems fine
  • Actuall hardware still glitched

ideas for the workshop

  • Fix core/vram/vga to get some real video output!
  • See if we can fit the vram by resizing things?

Also checkout The main project page