Difference between revisions of "PLD Workshop 2013/10/02"
From Hackerspace.gr
(→Stuff for review) |
|||
| (One intermediate revision by the same user not shown) | |||
| Line 19: | Line 19: | ||
''sdlcore @ [https://github.com/pld-lessons/simple_soc/blob/master/src/sdlcore/core.cpp github]'' | ''sdlcore @ [https://github.com/pld-lessons/simple_soc/blob/master/src/sdlcore/core.cpp github]'' | ||
| − | ''verilog WIP @ | + | ''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]'' |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
==== Plans for the workshop ==== | ==== Plans for the workshop ==== | ||
| Line 31: | Line 27: | ||
* Attach vga logic | * Attach vga logic | ||
| + | ==== Aftermath ==== | ||
| + | * Implemented ram using built in, block ram | ||
| + | * Added state logic for ram delays | ||
Also checkout [[Simple_SoC|The main project page]] | Also checkout [[Simple_SoC|The main project page]] | ||
Latest revision as of 14:18, 3 October 2013
 [Hackerspace.gr external link] |
Starts | Organizer |
|---|---|---|
| Wed 02 Oct 2013 19:30 | Hackerspace.gr | |
| Ends | Event Owner | |
| Wed 02 Oct 2013 21:30 | User:Skmp |
Howdy Simulator
Stuff for review
sdlcore @ github
verilog WIP @ github
Plans for the workshop
- Work a bit on the verilog code
- Load example program
- Simulate it
- Attach vga logic
Aftermath
- Implemented ram using built in, block ram
- Added state logic for ram delays
Also checkout The main project page
