PLD/FPGA Workshop 2.11

Simple soc logo.jpg


[Hackerspace.gr external link]
Starts Organizer
Error: Invalid time. Hackerspace.gr
Ends Event Owner
Error: Invalid time. User:Skmp

Debuggable Hardware







Useful Links

sdlcore @ github

verilog WIP @ github

ideas for the workshop

  • Work on the ICE implementation



Also checkout The main project page