PLD/FPGA Workshop 2.8
[Hackerspace.gr external link]
|Wed 13 Nov 2013 19:30||Hackerspace.gr|
|Wed 13 Nov 2013 21:30||User:Skmp|
Stuff for review
sdlcore @ github
verilog WIP @ github
- designed an ICE protocol to ease debugging
- Investigated UART
- Tested echo implementation at 3MBaud, worked nicely
- Investigated ISA
- 6 mhz looks plausible for interfacing (VGA/ETH)
ideas for the workshop
- think ways to update the program
- this is a must so we can test/develop faster
- Test/design validation "suite"?
- See why the simple tests don't work on the hardware
- But they work on the xilinx simulator. Some kind of corner case?
- take pictures
- cleanup repo ?
Also checkout The main project page